000 00462nam a2200181Ia 4500
008 180424s9999 xx 000 0 und d
020 _a9.79E+12
084 _a621.395 P6
100 _a"Palnitkar, Samir"
245 0 _aVerilog HDL:A Guide to Digital Design and Synthesis
250 _a\\201302ENGGPCX
260 _aAddison Wesley
260 _b2013
260 _cLondon
300 _a490p.
500 _aincludes index and biblioraphy
942 _cBK
999 _c100588
_d100588